1. Field
This disclosure relates generally to semiconductor devices, and more specifically, to a method for process integration of non-volatile memory (NVM) cell transistors with transistors of another type.
2. Related Art
Many semiconductor devices include, or embed, non-volatile memory transistors with other transistor types on the same integrated circuit (IC). The manufacturing processes for the different transistor types may not be the same, requiring that the processes be integrated. For example, to integrate NVM with, for example, CMOS (complementary metal oxide semiconductor), the CMOS process may be modified to include the process steps necessary to fabricate the NVM memory cell and the supporting devices such as peripheral high voltage (HV) transistors and low voltage (LV) transistors.
In most embedded NVMs, information is stored as charge on a “floating gate” which is completely surrounded by insulators, and which affects the threshold voltage of a transistor such that one bit of information corresponds to its on- and off-state. Charge is moved into and out of the floating gate by physical mechanisms such as hot-carrier injection or tunneling. Either method requires voltages higher than the core supply voltage. Using contemporary technology, a potential of approximately ±9 volts is required. To support these elevated voltages, the peripheral HV transistors are built with thicker-than-nominal gate oxides, and charge pump circuits are employed to generate the high voltages from the chip supply voltage.
Flash NVM is commonly embedded in, for example, system-on-a-chip (SoC) integrated circuits having both HV and LV transistors. In a semiconductor fabrication process for forming the embedded flash memory on an IC with HV transistors using two polysilicon layers, a first polysilicon layer may be used to form the non-volatile memory cell floating gates and the HV transistor gates. Or the first polysilicon layer may be used to form the memory cell floating gates while a second polysilicon layer is patterned to produce HV transistor gates. Additionally, the second polysilicon layer may also be used to form the LV transistor gates. The flash NVM may have an ONO (oxide-nitride-oxide) insulating layer between the floating gate and the control gate. The ONO layer is removed from the HV transistor gates. However, in some semiconductor fabrication processes undesirable ONO sidewall spacers may be formed on the sides of the HV transistor gates that are not easily removed. The presence of the ONO spacers may cause reliability issues with the HV transistors because charge traps in the nitride may cause unstable operation. An additional isotropic dry etch or an isotropic wet BOE (buffered oxide etchant) etch can be used to remove the ONO spacers. However, using an etch process to remove the ONO spacers adds additional process steps that increase manufacturing time and expense. Also, the unwanted ONO spacers on the sidewall can lift off during further processing, raising the level of contamination and defectivity for the semiconductor device.